This invention relates to digital data transmission, and more particularly to non-return to zero (NRZ) clock and data recovery.
NRZ data does not contain a spectral component at the clock frequency. Therefore, some way must be found to ascertain the clock signal frequency and phase. FIG. 1 shows one prior art approach to this problem. In this approach a non-linearity, in the form of a delay line and an exclusive-OR gate, is introduced to produce a frequency component at the NRZ clock frequency. The delay element is typically one half of the expected bit interval or less. A bandpass filter then detects the introduced frequency component at the clock frequency and either produces a clock directly or produces a clock indirectly with the assistance of a phase lock loop.
The difficulty with the approach shown in FIG. 1 and described above is that a bandpass filter does not lend itself to integration into an integrated circuit (IC), and the phase accuracy of the recovered clock depends on the tuning of the bandpass filter.
Another prior art approach is shown in FIG. 2. This approach does not require a tuned circuit and is therefore more amenable to IC implementation. However, the accuracy of the placement of the clock edge in the center of the bit interval depends primarily on the length of the delay line. In all of the typical IC implementations of a delay line, the amount of delay that results is subject to process and temperature variations. Thus, the clock edge is not well centered within the bit interval and, in the presence of significant jitter, the bit error rate suffers accordingly.
What is desired is an improved NRZ clock and data recovery system that lends itself to integration, that includes a phase and NRZ frequency detector and a lock detector, and that provides automatic centering of the clock edge within the bit interval in a manner that is independent of analog delays and process and temperature variations.